? semiconductor components industries, llc, 2012 may, 2012 ? rev. 2 1 publication order number: nup4114/d nup4114 series, SZNUP4114HMR6T1G transient voltage suppressors esd protection diodes with low clamping voltage the nup4114 transient voltage suppressors are designed to protect high speed data lines from esd. ultra ? low capacitance and high level of esd protection make these devices well suited for use in usb 2.0 high speed applications. features ? low clamping voltage ? small body outline dimensions on sc ? 88 package: 0.082 x 0.078 (2.10 mm x 1.25 mm) ? low body height: 0.043 (1.10 mm) ? stand ? off voltage: 5.5 v ? low leakage ? response time is typically < 1.0 ns ? iec61000 ? 4 ? 2 level 4 esd protection ? these devices are pb ? free and are rohs compliant ? aec ? q101 qualified and ppap capable ? sznup4114 ? sz prefix for automotive and other applications requiring unique site and control change requirements typical applications ? lvds ? usb 2.0 high speed data line and power line protection ? digital video interface (dvi) and hdmi ? monitors and flat panel displays ? high speed communication line protection ? notebook computers ? gigabit ethernet maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ? 40 to +125 c storage temperature range t stg ? 55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000 ? 4 ? 2 (esd) contact air 8 15 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. see application note and8308/d for further description of survivability specs. http://onsemi.com marking diagrams x2 m xxx = specific device code m = date code = pb ? free package 1 6 1 sc ? 88 w1 suffix case 419b (note: microdot may be in either location) 5 3 6 2 1 4 x4 m 1 6 1 sc ? 88 w1 suffix case 419b p4h m 1 6 tsop ? 6 case 318g style 12 1 sot ? 563 case 463a p4m 1 1 6 see detailed ordering and shipping information in the package dimensions sect ion on page 4 of this data sheet. ordering information
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current i f forward current v f forward voltage @ i f p pk peak power dissipation c capacitance @ v r = 0 and f = 1.0 mhz *see application note and8308/d for detailed explanations of datasheet parameters. uni ? directional tvs i pp i f v i i r i t v rwm v c v br v f electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm (note 1) 5.5 v breakdown voltage v br i t = 1 ma, (note 2) 5.5 v reverse leakage current i r v rwm = 5.5 v 1.0 a clamping voltage v c i pp = 5 a (note 3) 9.0 v clamping voltage v c i pp = 8 a (note 3) 10 v clamping voltage v c i pp = 1 a (note 4) 8.3 10 v esd clamping voltage v c per iec61000 ? 4 ? 2 (note 5) see figures 1 & 2 maximum peak pulse current i pp 8x20 s waveform (note 3) 12 a junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd 0.6 pf junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins 0.3 pf 1. tvs devices are normally selected according to the working peak reverse voltage (v rwm ), which should be equal or greater than the dc or continuous peak operating voltage level. 2. v br is measured at pulse test current i t . 3. nonrepetitive current pulse (pin 5 to pin 2) 4. nonrepetitive current pulse (i/o to gnd). 5. for test procedure see figures 3 and 4 and application note and8307/d. 6. include sz ? prefix devices where applicable. figure 1. esd clamping voltage screenshot positive 8 kv contact per iec61000 ? 4 ? 2 figure 2. esd clamping voltage screenshot negative 8 kv contact per iec61000 ? 4 ? 2
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 3 iec 61000 ? 4 ? 2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000 ? 4 ? 2 spec figure 4. diagram of esd test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d. figure 5. 8 x 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 020406080 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 4 figure 6. 500 mhz data pattern ordering information device marking package shipping ? nup4114uclw1t2g x2 sc ? 88 (pb ? free) 3000 / tape & reel nup4114ucw1t2g x4 sc ? 88 (pb ? free) 3000 / tape & reel nup4114upxv6t1g p4 sot ? 563 (pb ? free) 4000 / tape & reel nup4114hmr6t1g p4h tsop ? 6 (pb ? free) 3000 / tape & reel SZNUP4114HMR6T1G p4h tsop ? 6 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 5 applications information the new nup4114 is a low capacitance tvs diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to esd events or transient overvoltage conditions. because of its low capacitance, it can be used in high speed i/o data lines. the integrated design of the nup4114 offers low capacitance steering diodes and a tvs diode integrated in a single package (tsop ? 6). if a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. the tvs device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. nup4114 configuration options the nup4114 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. the steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (v f or v cc + v f ). the diodes will force the transient current to bypass the sensitive circuit. data lines are connected at pins 1, 3, 4 and 6. the negative reference is connected at pin 2. this pin must be connected directly to ground by using a ground plane to minimize the pcb?s ground inductance. it is very important to reduce the pcb trace lengths as much as possible to minimize parasitic inductances. option 1 protection of four data lines and the power supply using v cc as reference. i/o 1 i/o 2 i/o 3 i/o 4 v cc 6 5 4 1 2 3 for this configuration, connect pin 5 directly to the positive supply rail (v cc ), the data lines are referenced to the supply voltage. the internal tvs diode prevents overvoltage on the supply rail. biasing of the steering diodes reduces their capacitance. option 2 protection of four data lines with bias and power supply isolation resistor. v cc 10 k i/o 1 i/o 2 i/o 3 i/o 4 6 5 4 1 2 3 the nup4114 can be isolated from the power supply by connecting a series resistor between pin 5 and v cc . a 10 k resistor is recommended for this application. this will maintain a bias on the internal tvs and steering diodes, reducing their capacitance. option 3 protection of four data lines using the internal tvs diode as reference. i/o 1 i/o 2 i/o 3 i/o 4 nc 6 5 4 1 2 3 in applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal tvs can be used as the reference. for these applications, pin 5 is not connected. in this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the tvs plus one diode drop (v c = v f + v tvs ). esd protection of power supply lines when using diodes for data line protection, referencing to a supply rail provides advantages. biasing the diodes reduces their capacitance and minimizes signal distortion.
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 6 implementing this topology with discrete devices does have disadvantages. this configuration is shown below: v cc d1 d2 data line i esdpos i esdneg vf + v cc ? vf i esdpos i esdneg power supply protected device looking at the figure above, it can be seen that when a positive esd condition occurs, diode d1 will be forward biased while diode d2 will be forward biased when a negative esd condition occurs. for slower transient conditions, this system may be approximated as follows: for positive pulse conditions: v c = v cc + v fd1 for negative pulse conditions: v c = ? v fd2 esd events can have rise times on the order of some number of nanoseconds. under these conditions, the effect of parasitic inductance must be considered. a pictorial representation of this is shown below. v cc d1 d2 data line i esdpos i esdneg v c = v cc + vf + (l diesd/dt) i esdpos i esdneg power supply protected device v c = ? vf ? (l diesd/dt) an approximation of the clamping voltage for these fast transients would be: for positive pulse conditions: v c = v cc + vf + (l di esd /dt) for negative pulse conditions: v c = ? v f ? (l di esd /dt) as shown in the formulas, the clamping voltage (v c ) not only depends on the vf of the steering diodes but also on the l di esd /dt factor. a relatively small trace inductance can result in hundreds of volts appearing on the supply rail. this endangers both the power supply and anything attached to that rail. this highlights the importance of good board layout. taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. even with good board layout, some disadvantages are still present when discrete diodes are used to suppress esd events across datalines and the supply rail. discrete diodes with good transient power capability will have larger die and therefore higher capacitance. this capacitance becomes problematic as transmission frequencies increase. re ducing capacitance generally requires reducing die size. these small die will have higher forward voltage characteristics at typical esd transient current levels. this voltage combined with the smaller die can result in device failure. the on semiconductor nup4114 was developed to overcome the disadvantages encountered when using discrete diodes for esd protection. this device integrates a tvs diode within a network of steering diodes. figure 7. nup4114 equivalent circuit 5 3 6 2 1 4 during an esd condition, the esd current will be driven to ground through the tvs diode as shown below. v cc d1 d2 data line i esdpos power supply protected device the resulting clamping voltage on the protected ic will be: v c = v f + v tvs . the clamping voltage of the tvs diode depends on the magnitude of the esd current. the steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics.
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 7 package dimensions ? 6 case 318g ? 02 issue u 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 8 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. 419b ? 01 obsolete, new standard 419b ? 02. e 0.2 (0.008) mm 123 d e a1 a a3 c l 654 ? e ? b 6 pl sc ? 88/sc70 ? 6/sot ? 363 case 419b ? 02 issue w dim min nom max millimeters a 0.80 0.95 1.10 a1 0.00 0.05 0.10 a3 b 0.10 0.21 0.30 c 0.10 0.14 0.25 d 1.80 2.00 2.20 0.031 0.037 0.043 0.000 0.002 0.004 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 min nom max inches 0.20 ref 0.008 ref h e h e e 1.15 1.25 1.35 e 0.65 bsc l 0.10 0.20 0.30 2.00 2.10 2.20 0.045 0.049 0.053 0.026 bsc 0.004 0.008 0.012 0.078 0.082 0.086 mm inches scale 20:1 0.65 0.025 0.65 0.025 0.50 0.0197 0.40 0.0157 1.9 0.0748 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* sc ? 88/sc70 ? 6/sot ? 363
nup4114 series, SZNUP4114HMR6T1G http://onsemi.com 9 package dimensions h e dim min nom max millimeters a 0.50 0.55 0.60 b 0.17 0.22 0.27 c d 1.50 1.60 1.70 e 1.10 1.20 1.30 e 0.5 bsc l 0.10 0.20 0.30 1.50 1.60 1.70 0.020 0.021 0.023 0.007 0.009 0.011 0.059 0.062 0.066 0.043 0.047 0.051 0.02 bsc 0.004 0.008 0.012 0.059 0.062 0.066 min nom max inches sot ? 563, 6 lead case 463a ? 01 issue f e m 0.08 (0.003) x b 6 5 pl a c ? x ? ? y ? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. d e y 12 3 4 5 l 6 1.35 0.0531 0.5 0.0197 mm inches scale 20:1 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h e 0.08 0.12 0.18 0.003 0.005 0.007 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. nup4114/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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